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Development of Multiobjective High-Level Synthesis for FPGAs
Scientific Programming ( IF 1.672 ) Pub Date : 2020-06-29 , DOI: 10.1155/2020/7095048
Darian Reyes Fernandez de Bulnes 1 , Yazmin Maldonado 1 , Leonardo Trujillo 1
Affiliation  

Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

中文翻译:

FPGA 多目标高级综合的开发

传统上,现场可编程门阵列 (FPGA) 设备的高级综合 (HLS) 是一种将行为描述(作为与时序无关的规范)转换为可综合的抽象级别(如寄存器传输级别)的方法。这个过程可以在称为设计空间探索 (DSE) 的框架下执行,它通过解决调度、分配和绑定问题来帮助确定最佳设计,这三个问题都是 NP 难题。以这种方式,并且由于现代数字电路设计的复杂性增加以及对 FPGA 容量的关注,设计人员提出了能够执行自动优化的新型 HLS 技术。HLS 有几个相互冲突的指标或目标函数,例如延迟、面积、功率、线长、数字噪声、可靠性和安全性。出于这个原因,适合应用多目标优化算法(MOA),它可以处理目标函数之间的不同权衡。在过去的二十年中,已经应用了几种 MOA 来解决这个问题。本文介绍了适用于对 FPGA 设备执行 HLS 的不同 MOA 的综合分析。我们强调了 MOA 的重要方面,即优化方法、执行优化的中间结构、解决的 HLS 技术以及用于实验的基准和性能评估。此外,我们还分析了当前算法中如何优化多个目标以及优化了哪些目标函数。最后,
更新日期:2020-06-29
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