This report shows packaging‐induced stress distribution of a small‐scale silicon chip encapsulated by a Small‐Outline Nonleaded package. The proposed method made it possible to visualize the stress distribution chart for a chip about 1.0 mm² in size with high accuracy, even when the chip has only four pads. It is found that the stress was generated during resin molding, as determined from stress measurement during the middle of the packaging process. In addition, the impact of filler particle size and position in Epoxy Molding Compounds on the local stress of the chip surface is revealed. The compressive stresses were found to be greatest at the center of the chip and gradually decrease toward the edges. Also, the results for die pad structure produced a characteristic distribution chart in which the central area of the silicon chip has a smaller stress gradient. The impact of high‐temperature storage test on residual stress is also discussed. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

中文翻译：

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小型硅芯片封装引起的应力分布的表征

该报告显示了由小型无铅封装封装的小型硅芯片的封装引起的应力分布。所提出的方法可以可视化约1.0 mm ²的芯片的应力分布图即使芯片只有四个焊盘，其尺寸也具有很高的精度。已经发现，应力是在树脂模制期间产生的，这是根据包装过程中途的应力测量确定的。此外，揭示了环氧树脂模塑料中填料粒径和位置对芯片表面局部应力的影响。发现压应力在切屑的中心处最大，并向边缘逐渐减小。而且，管芯焊盘结构的结果产生了特性分布图，其中硅芯片的中心区域具有较小的应力梯度。还讨论了高温存储测试对残余应力的影响。©2020日本电气工程师学会。由Wiley Periodicals LLC发布。