To preserve the SystemC semantics under parallel discrete event simulation, a compiler based approach statically analyzes race conditions in the design model. However, there are severe restrictions: the source code for the input design must be available in one file, which does not scale. This disables the use of intellectual property (IP) and hierarchical file structures. This paper scales the static analysis design flow to support separate files and IP reuse by introducing partial segment graph and partial port mapping abstractions and prevent IP security leakage. Experiments demonstrate the effective design flow and sustained speedup with parallel IPs.

中文翻译：

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用于无序并行 SystemC 仿真的缩放静态分析和 IP 重用

为了在并行离散事件仿真下保留 SystemC 语义，基于编译器的方法静态分析设计模型中的竞争条件。但是，有严格的限制：输入设计的源代码必须在一个文件中可用，该文件不可扩展。这禁用了知识产权 (IP) 和分层文件结构的使用。本文通过引入部分段图和部分端口映射抽象来扩展静态分析设计流程以支持单独的文件和 IP 重用，并防止 IP 安全泄漏。实验证明了并行 IP 的有效设计流程和持续加速。