This paper presents a 12-bit branching Time-to-Digital converter (TDC) fabricated in a 40 nm CMOS technology. It composes of a 6-bit coarse counter TDC, and a 6-bit fine TDC. The fine TDC utilizes a proposed branching technique to interpolate between the phases of a 16-stage gated ring oscillator, increasing its number of phases from 16 to 64. Therefore, the TDC resolution is improved to be 4 times finer. The TDC incorporates fully digital based resolution tuning capability that enables its resolution to be more stable over PVT variations. Measurement results show that the resolution tuning reduces the resolution variation by 92.3% over a temperature range of − 40 to 125 °C. However, the simple resolution tuning method causes the TDC to have a relatively large resolution of 36.2 ps. The trade-offs between TDC resolution, yield, and scalability are discussed. The proposed TDC uses simple gated inverters based samplers instead of conventional arbiters to reduce power and area consumption. In addition, power gating features of the proposed TDC enable a low power consumption of 275 µW at a sampling rate of 5 MS/s. Without any linearity calibrations, the TDC DNL, INL, single-shot precision, and figure-of-merit are measured to be 1.30 LSB, 3.61 LSB, 0.75 LSB, and 61.9 fJ/conv.-step, respectively.

本文提出了一种采用40 nm CMOS技术制造的12位分支时间数字转换器（TDC）。它由一个6位粗略计数器TDC和一个6位精细TDC组成。精细的TDC利用提议的分支技术在16级门控环形振荡器的相位之间进行插值，从而将其相位数从16增加到64。因此，TDC分辨率提高了4倍。TDC具有完全基于数字的分辨率调整功能，可使其分辨率在PVT变化范围内更加稳定。测量结果表明，在− 40至125°C的温度范围内，分辨率调整可将分辨率变化降低92.3％。但是，简单的分辨率调整方法会使TDC具有36.2 ps的相对较大的分辨率。TDC分辨率，良率，讨论了可扩展性。提议的TDC使用基于简单门控反相器的采样器，而不是传统的仲裁器，以减少功耗和面积消耗。此外，建议的TDC的功率门控功能可在5 MS / s的采样率下实现275 µW的低功耗。在没有任何线性校准的情况下，TDC DNL，INL，单次精度和品质因数分别被测量为1.30 LSB，3.61 LSB，0.75 LSB和61.9 fJ / conv.-step。