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DPL-Based Novel CMOS 1-Trit Ternary Full-Adder
International Journal of Electronics ( IF 1.1 ) Pub Date : 2020-07-09 , DOI: 10.1080/00207217.2020.1789759
Aloke Saha 1 , Rakesh Kumar Singh 1 , Pragya Gupta 1 , Dipankar Pal 2
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This paper presents a new high-speed, low-power, area-efficient 1-trit Ternary-Full-Adder (TFA) as a building block for wave-pipelined ternary-digital system design. Balanced input capacitance with...

中文翻译:

基于 DPL 的新型 CMOS 1-Trit 三元全加器

本文介绍了一种新的高速、低功耗、面积高效的 1-trit 三元全加器 (TFA),作为波流水线三元数字系统设计的构建块。平衡输入电容...
更新日期:2020-07-09
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