A parallel-MOS-triggered silicon-controlled rectifier (PMTSCR) is firstly proposed and verified in a 0.25-μm Bipolar-CMOS-DMOS process, aiming to prevent the latch-up effect of SCR in the electrostatic discharge (ESD) protection. Comparing to the conventional SCR, the trigger voltage (V_t1) of the PMTSCR decreases because of the effect of PMOS embedded in the N-well, and the holding voltage (V_h) increases because of the attribution of the NMOS embedded in the P-well. By shortening the SCR current conduction path and designing a special metal connection, the modified-PMTSCR (M-PMTSCR) is obtained. The failure current of the M-PMTSCR remarkably increases from 1.8 to 4.8 A. However, M-PMTSCR exhibits a lower V_h and a higher V_t1. By further optimizing the location and connection of the embedded PMOS and NMOS, the obtained cascade-MOS-triggered SCR (CMTSCR) possesses a high V_h of 8.4 V and a strong ESD robustness of 6000 V in a small chip area. Meanwhile, the operation mechanism simulated by Sentaurus was consistent with the theoretical circuit analysis and transmission line pulse measurements. Thus the proposed CMTSCR with the good latch up immunity and temperature stability is a promising device to meet the requirements of high voltage ESD protection.

首次提出并在0.25μm双极CMOS-DMOS工艺中验证了并联MOS触发的可控硅整流器（PMTSCR），目的是防止SCR在静电放电（ESD）保护中的闩锁效应。与传统的SCR相比，PMTSCR的触发电压（V _{t 1}）由于嵌入在N阱中的PMOS的影响而降低，并且保持电压（V _h）由于嵌入在N阱中的NMOS的特性而增加。 P井。通过缩短SCR电流传导路径并设计特殊的金属连接，可以获得改进的PMTSCR（M-PMTSCR）。M-PMTSCR的故障电流从1.8 A显着增加到4.8A。但是，M-PMTSCR的V _h较低和较高的V_吨1.通过进一步优化位置和嵌入的PMOS和NMOS，将得到的级联-MOS触发SCR（CMTSCR）的连接具有高的V _ħ 8.4伏的并且在6000 V的强ESD鲁棒性芯片面积小。同时，Sentaurus模拟的工作机制与理论电路分析和传输线脉冲测量结果一致。因此，所提出的具有良好的抗闩锁性和温度稳定性的CMTSCR是满足高压ESD保护要求的有前途的器件。