As technology evolves, new devices emerge to overcome the known short-channel effects of conventional MOSFETs. FinFETs, as recent devices, are widely used in modern processor designs. Elaborate design of circuit elements can effectively increase the overall chip performance. In this paper we studied the design of high performance flip-flop (FF) using FinFET devices. We have investigated several transistor sizing methods in FinFET technology to design the FF circuit based on different input and output capacitances. The results indicate that the circuit designed using minimum-energy-delay-area product (min-EDAP) approach has the lowest PDP. We developed a modified logical effort approach that leads to a minimum EDP design compared to the other approaches. The performance of flip-flop is also investigated based on the metrics extracted from energy efficient curve (EEC). Results show that the ED metric has the minimum EDP in all cases. Moreover, the E⁴D metric shows the least variations against frequency and voltage fluctuations, while the ED⁴ metric is more robust against temperature variations. Simulations are performed using HSPICE in 16 nm FinFET technology with shorted-gate (SG) mode configuration.

随着技术的发展，出现了新的器件来克服传统MOSFET的已知短沟道效应。FinFET作为最新的器件，已广泛用于现代处理器设计中。精心设计的电路元件可以有效提高整体芯片性能。在本文中，我们研究了使用FinFET器件的高性能触发器（FF）的设计。我们研究了FinFET技术中的几种晶体管尺寸确定方法，以基于不同的输入和输出电容设计FF电路。结果表明，使用最小能量延迟面积积（min-EDAP）方法设计的电路具有最低的PDP。我们开发了一种改进的逻辑努力方法，与其他方法相比，该方法可将EDP设计降至最低。还基于从能效曲线（EEC）中提取的指标来研究触发器的性能。结果表明，在所有情况下，ED指标具有最小的EDP。而且，E⁴ D度量标准显示出对频率和电压波动的最小变化，而ED ⁴度量标准则对温度变化更稳定。使用具有短栅（SG）模式配置的16 nm FinFET技术中的HSPICE进行仿真。