This paper presents the characterization results and the experimental evaluation of a test chip imager development, employing column-parallel oversampling converters as a means to mitigate both thermal and flicker noise contributions, by using specifically noise-shaping single-bit incremental converters to provide low output noise digital samples in a short period of time. The main goal of this paper is present the fabricated imager based on the designed signal converter type and to use such types of converters in a future test chip development that ultimately can reach sub-electron system readout noise performance. Lastly, this research paper shows the measured performance of the developed 14-bit incremental converter-based imager with 1% system non-linearity, 700mV+ ADC input range and 2.67e- and 3.85e- total readout chain input-referred electrical and input-referred optical readout noise, respectively. The sensor was fabricated with a Tower Jazz 180nm Image Sensor Process Development Kit, namely the TS18IS 4M1L module, allowing for 1.8V/3.3V devices, 4 metal layers and Well-buried devices – the Triple Well process.

本文介绍了测试芯片成像器开发的表征结果和实验评估，通过使用专为噪声整形的单比特增量式转换器提供低输出，采用列并行过采样转换器作为缓解热噪声和闪烁噪声的一种方法在短时间内噪声数字采样。本文的主要目的是提出一种基于设计的信号转换器类型的预制成像仪，并在未来的测试芯片开发中使用此类转换器，最终可以达到亚电子系统读出噪声性能。最后，本研究论文展示了已开发的基于14位增量转换器的成像器的测量性能，该成像器具有1％的系统非线性度，700mV + ADC输入范围以及2.67e-和3。85e-总读出链输入参考电和输入参考光学读出噪声。该传感器是使用Tower Jazz 180nm图像传感器工艺开发套件（即TS18IS 4M1L模块）制造的，可用于1.8V / 3.3V器件，4个金属层和埋入式器件-三阱工艺。