In recent years, Physically Unclonable Functions (PUFs) have emerged as a promising technique for hardware based security primitives because of its inherent uniqueness and low cost. In this paper, we present an area efficient hybrid PUF design on field-programmable gate array (FPGA). Our approach combines units of conventional RS Latch-based PUF (RS-LPUF) and Arbiter-based PUF (A-PUF) which is then augmented by the programmable delay lines (PDLs) and Temporal Majority Voting (TMV) for performance enhancement. The area of the hybrid PUF is relatively high when compared to few conventional PUF designs, but is significantly small when compared to other composite and hybrid PUF designs reported so far. The measured results on the Xilinx Spartan-6 FPGA demonstrate PUF signatures exhibits good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing.

近年来，物理上不可克隆的功能（PUF）由于其固有的唯一性和低成本而成为基于硬件的安全原语的一种有前途的技术。在本文中，我们提出了一种基于现场可编程门阵列（FPGA）的区域高效混合PUF设计。我们的方法将传统的基于RS闩锁的PUF（RS-LPUF）和基于仲裁器的PUF（A-PUF）结合在一起，然后通过可编程延迟线（PDL）和临时多数投票（TMV）进行增强，以提高性能。与少数传统PUF设计相比，混合PUF的面积相对较高，但与迄今为止报道的其他复合和混合PUF设计相比，其面积却很小。在Xilinx Spartan-6 FPGA上的测量结果表明，PUF签名具有良好的唯一性，可靠性，