While neural network models keep scaling in depth and computational requirements, biologically accurate models are becoming more interesting for low-cost inference. Coupled with the need to bring more computation to the edge in resource-constrained embedded and IoT devices, specialized ultra-low power accelerators for spiking neural networks are being developed. Having a large variance in the models employed in these networks, these accelerators need to be flexible, user-configurable, performant and energy efficient. In this paper, we describe CyNAPSE, a fully digital accelerator designed to emulate neural dynamics of diverse spiking networks. Since the use case of our implementation is primarily concerned with energy efficiency, we take a closer look at the factors that could improve its energy consumption. We observe that while majority of its dynamic power consumption can be credited to memory traffic, its on-chip components suffer greatly from static leakage. Given that the event-driven spike processing algorithm is naturally memory-intensive and has a large number of idle processing elements, it makes sense to tackle each of these problems towards a more efficient hardware implementation. With a diverse set of network benchmarks, we incorporate a detailed study of memory patterns that ultimately informs our choice of an application-specific network-adaptive memory management strategy to reduce dynamic power consumption of the chip. Subsequently, we also propose and evaluate a leakage mitigation strategy for runtime control of idle power. Using both the RTL implementation and a software simulation of CyNAPSE, we measure the relative benefits of these undertakings. Results show that our adaptive memory management policy results in up to 22% more reduction in dynamic power consumption compared to conventional policies. The runtime leakage mitigation techniques show that up to 99.92% and at least 14% savings in leakage energy consumption is achievable in CyNAPSE hardware modules.

尽管神经网络模型在深度和计算要求上不断扩大规模，但生物学上准确的模型对于低成本推理正变得越来越有趣。加上在资源受限的嵌入式和IoT设备中将更多计算带到边缘的需求，正在开发用于加标神经网络的专用超低功耗加速器。这些加速器的模型差异很大，因此这些加速器需要灵活，用户可配置，高性能和高能效。在本文中，我们描述了CyNAPSE，这是一种全数字加速器，旨在模拟各种尖峰网络的神经动力学。由于我们实施的用例主要涉及能源效率，因此我们仔细研究可以改善其能源消耗的因素。我们观察到，虽然其大部分动态功耗可以归因于内存流量，但其片上组件却遭受了静态泄漏的严重困扰。鉴于事件驱动的尖峰处理算法自然是内存密集型的，并且具有大量的空闲处理元素，因此有必要解决这些问题，以实现更高效的硬件实现。借助各种网络基准测试，我们结合了对内存模式的详细研究，最终为我们选择了特定于应用程序的网络自适应内存管理策略提供了信息，以减少芯片的动态功耗。随后，我们还提出并评估了泄漏缓解策略，用于对空闲电源进行运行时控制。同时使用RTL实现和CyNAPSE的软件仿真，我们衡量这些事业的相对利益。结果表明，与传统策略相比，我们的自适应内存管理策略可将动态功耗降低多达22％。运行时泄漏缓解技术表明，在CyNAPSE硬件模块中，可实现高达99.92％的泄漏能耗节省和至少14％的节省。