A dual-channel single gate junctionless FET (DCJLT) is investigated to improve the analog/RF performance. The gate of proposed structure is placed in a vertical trench and two channels are taken on both sides of the gate. The proposed device is studied with moderate and heavily doped drain concentrations which are named as MDD-DCJLT and HDD-DCJLT, respectively. The performance parameters of both devices are evaluated and compared in terms of drain current (I_DS), transconductance (g_m), transconductance generation efficiency (g_m/I_DS), unity-gain cut-off frequency (f_T) and maximum oscillation frequency (f_max) using 2D numerical simulations in a TCAD tool (ATLAS). The proposed HDD-DCJLT is demonstrated to offer peak g_m, f_T and f_max of 2304 μS/μm, 548 GHz and 830 GHz, respectively at gate length of 20 nm. Thus, the proposed structure is a suitable choice for analog/RF applications.

研究了双通道单栅极无结FET（DCJLT），以改善模拟/ RF性能。所提出的结构的栅极放置在垂直沟槽中，并且在栅极的两侧采用两个沟道。研究了拟议的器件，并以中等浓度和重掺杂的漏极浓度对它们进行了命名，分别称为MDD-DCJLT和HDD-DCJLT。评估并比较了两种器件的性能参数，分别以漏极电流（I _{D S}），跨导（g _m），跨导产生效率（g _m / I _{D S}），单位增益截止频率（f _T）进行比较。和最大振荡频率（f_{m a x}）在TCAD工具（ATLAS）中使用2D数值模拟。所提出的HDD-DCJLT被证明提供峰克_米， ˚F _Ť和˚F_米一个X 2304 μ小号/ μ米，548千兆赫和830千兆赫，分别以20nm的栅极长度。因此，提出的结构是模拟/ RF应用的合适选择。