To meet ever increasing demand for performance of emerging System-on-Chip (SoC) applications, designer employ techniques for concurrent communication between components. Hence communication architecture becomes complex and major performance bottleneck. An early performance evaluation of communication architecture is the key to reduce design time, time-to-market and consequently cost of the system. Moreover, it helps to optimize system performance by selecting appropriate communication architecture. However, performance model of concurrent communication is complex to describe and hard to solve. In this paper, we propose methodology for performance evaluation of bus based communication architectures, modeling for which is based on modular Stochastic Automata Network (SAN). We employ Generalized Semi Markov Process (GSMP) model for each module of the SAN that emulates dynamic behavior of a Processing Element (PE) of an SoC architecture. The proposed modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element; while we provide parameters viz. number of processing elements, the mean computation time of processing elements and the first and second moments of connection time between processing elements and memories, as input to the model.

中文翻译：

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用于异构 SoC 通信性能评估的随机自动机网络

为了满足对新兴片上系统 (SoC) 应用程序性能不断增长的需求，设计人员采用了组件之间的并发通信技术。因此通信架构变得复杂并且是主要的性能瓶颈。通信架构的早期性能评估是减少设计时间、上市时间以及系统成本的关键。此外，它有助于通过选择合适的通信架构来优化系统性能。然而，并发通信的性能模型描述复杂且难以解决。在本文中，我们提出了基于总线的通信架构的性能评估方法，其建模基于模块化随机自动机网络（SAN）。我们对 SAN 的每个模块采用广义半马尔可夫过程 (GSMP) 模型，模拟 SoC 架构的处理元件 (PE) 的动态行为。所提出的建模方法提供了性能参数的早期估计，即。内存带宽、内存中的平均队列长度和处理元素看到的平均等待时间；而我们提供参数即。处理单元的数量、处理单元的平均计算时间以及处理单元和存储器之间连接时间的第一和第二时刻，作为模型的输入。内存中的平均队列长度和处理元素看到的平均等待时间；而我们提供参数即。处理单元的数量、处理单元的平均计算时间以及处理单元和存储器之间连接时间的第一和第二时刻，作为模型的输入。内存中的平均队列长度和处理元素看到的平均等待时间；而我们提供参数即。处理单元的数量、处理单元的平均计算时间以及处理单元和存储器之间连接时间的第一和第二时刻，作为模型的输入。