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Improving Dependability of Neuromorphic Computing With Non-Volatile Memory
arXiv - CS - Hardware Architecture Pub Date : 2020-06-10 , DOI: arxiv-2006.05868
Shihao Song, Anup Das, Nagarajan Kandasamy

As process technology continues to scale aggressively, circuit aging in a neuromorphic hardware due to negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) is becoming a critical reliability issue and is expected to proliferate when using non-volatile memory (NVM) for synaptic storage. This is because an NVM requires high voltage and current to access its synaptic weight, which further accelerates the circuit aging in a neuromorphic hardware. Current methods for qualifying reliability are overly conservative, since they estimate circuit aging considering worst-case operating conditions and unnecessarily constrain performance. This paper proposes RENEU, a reliability-oriented approach to map machine learning applications to neuromorphic hardware, with the aim of improving system-wide reliability without compromising key performance metrics such as execution time of these applications on the hardware. Fundamental to RENEU is a novel formulation of the aging of CMOS-based circuits in a neuromorphic hardware considering different failure mechanisms. Using this formulation, RENEU develops a system-wide reliability model which can be used inside a design-space exploration framework involving the mapping of neurons and synapses to the hardware. To this end, RENEU uses an instance of Particle Swarm Optimization (PSO) to generate mappings that are Pareto-optimal in terms of performance and reliability. We evaluate RENEU using different machine learning applications on a state-of-the-art neuromorphic hardware with NVM synapses. Our results demonstrate an average 38\% reduction in circuit aging, leading to an average 18% improvement in the lifetime of the hardware compared to current practices. RENEU only introduces a marginal performance overhead of 5% compared to a performance-oriented state-of-the-art.

中文翻译:

使用非易失性记忆提高神经形态计算的可靠性

随着工艺技术继续积极扩展,由于负偏置温度不稳定性 (NBTI) 和时间相关介电击穿 (TDDB) 导致的神经形态硬件中的电路老化正成为一个关键的可靠性问题,并且预计在使用非易失性存储器时会激增。 NVM)用于突触存储。这是因为 NVM 需要高电压和电流来访问其突触权重,这进一步加速了神经形态硬件中的电路老化。当前用于验证可靠性的方法过于保守,因为它们在考虑最坏情况下的工作条件和不必要地限制性能的情况下估计电路老化。本文提出了 RENEU,一种将机器学习应用程序映射到神经形态硬件的面向可靠性的方法,目的是在不影响关键性能指标的情况下提高系统范围的可靠性,例如这些应用程序在硬件上的执行时间。RENEU 的基础是考虑不同故障机制的神经形态硬件中基于 CMOS 的电路老化的新公式。使用此公式,RENEU 开发了一个系统范围的可靠性模型,该模型可在涉及神经元和突触到硬件的映射的设计空间探索框架内使用。为此,RENEU 使用粒子群优化 (PSO) 实例来生成在性能和可靠性方面是帕累托最优的映射。我们在具有 NVM 突触的最先进神经形态硬件上使用不同的机器学习应用程序评估 RENEU。我们的结果表明电路老化平均减少 38%,与当前做法相比,硬件寿命平均提高了 18%。与面向性能的最新技术相比,RENEU 仅引入了 5% 的边际性能开销。
更新日期:2020-06-11
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