This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation ( $$F_{\max }$$ F max ) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 $$\upmu $$ μ W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 $$\upmu {\text {m}}^2$$ μ m 2 .

中文翻译：

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一种用于电荷泵锁相环的无死区零盲区高速鉴频器

本文提出了一种新的相位频率检测器 (PFD) 架构，它消除了电荷泵锁相环 (CP-PLL) 的盲​​区效应和死区。该 PFD 采用 65 nm CMOS 技术设计，其功能在工艺、电压和温度变化范围内得到验证。实现的最大工作频率 ( $$F_{\max }$$ F max ) 为 3.44 GHz，适用于高参考时钟快速稳定 PLL。建议的 PFD 在最大工作频率下从 1.2 V 电源消耗 324 $$\upmu $$ μ W 功率。提议的电路布局占用的面积为 322.612 $$\upmu {\text {m}}^2$$ μ m 2 。