The in-memory computation of logic operations is a promising paradigm that could enable the development of highly efficient computing architectures, ideal for battery-powered devices. Indeed, Resistive Random Access Memory (RRAM) devices and the material implication logic (IMPLY) have been experimentally demonstrated to enable low-power logic-in-memory (LIM) circuits. Still, device and circuit non-idealities (e.g., the strong sensitivity to driving voltage variations) introduce several reliability challenges that must be addressed with appropriate device models. Often, general-purpose or simplified models are used in the analysis, thus resulting in questionable estimations and designs. In this work, we use a physics-based RRAM compact model, comprehensive of device non-idealities, to study the reliability of IMPLY-based LIM circuits. The analysis is first performed on the single IMPLY logic gate and then extended to an array implementation encompassing the effect of line parasitic resistances and node capacitances. We determine and quantitatively evaluate important metrics such as energy consumption and maximum array size, and derive appropriate design strategies aimed at improving the reliability of such circuits.

中文翻译：

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内存中状态逻辑架构的可靠性感知设计策略

逻辑运算的内存计算是一种很有前途的范例，可以开发高效的计算架构，非常适合电池供电的设备。事实上，电阻式随机存取存储器 (RRAM) 设备和材料隐含逻辑 (IMPLY) 已通过实验证明可以实现低功耗存储器逻辑 (LIM) 电路。尽管如此，设备和电路的非理想性（例如，对驱动电压变化的强烈敏感性）引入了几个必须通过适当的设备模型解决的可靠性挑战。通常，在分析中使用通用或简化模型，从而导致有问题的估计和设计。在这项工作中，我们使用基于物理的 RRAM 紧凑模型，综合了设备的非理想性，来研究基于 IMPLY 的 LIM 电路的可靠性。分析首先在单个 IMPLY 逻辑门上执行，然后扩展到包含线路寄生电阻和节点电容影响的阵列实现。我们确定并定量评估能耗和最大阵列尺寸等重要指标，并得出旨在提高此类电路可靠性的适当设计策略。