The digital designs operating in sub/near-threshold region are susceptible to timing errors due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper proposes a new error-detecting latch (EDL) to mitigate the impact of PVT variations. The proposed EDL is a single-phase clocked design, which significantly reduces the clock power consumption of the design. The proposed EDL follows a merged and shared architecture of two latches along with an XNOR gate, which leads to a compact layout of EDL. The post-layout simulations in an industrial 28 nm CMOS technology node, show a minimum clock power savings of 31%, average power savings of 16%, and reduction in leakage power by 23% in comparison to the state-of-the-art EDLs at 0.4 V. The 10K rigorous Monte-Carlo simulations across the supply voltage range of 0.23 V - 0.8 V and clock frequency range of 1.6 MHz - 70 MHz shows that the proposed EDL is tolerant to leakage-induced false errors and glitches. SSEDL is robust to process variations even with minimum-sized transistors.

中文翻译：

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用于亚/近阈值应用的泄漏引起的容错错误检测锁存器的设计和分析


由于工艺、电压和温度 (PVT) 变化的极端影响，在亚阈值/近阈值区域运行的数字设计很容易出现时序错误。本文提出了一种新的错误检测锁存器（EDL）来减轻 PVT 变化的影响。所提出的 EDL 是单相时钟设计，可显着降低设计的时钟功耗。所提出的 EDL 遵循两个锁存器和 XNOR 门的合并和共享架构，从而实现 EDL 的紧凑布局。工业 28 nm CMOS 技术节点的布局后仿真显示，与最先进的技术相比，最​​低时钟功耗可节省 31%，平均功耗可节省 16%，漏电功耗可减少 23% EDL 电压为 0.4 V。在 0.23 V - 0.8 V 电源电压范围和 1.6 MHz - 70 MHz 时钟频率范围内进行的 10K 严格蒙特卡罗仿真表明，所提出的 EDL 能够容忍泄漏引起的错误错误和毛刺。即使对于最小尺寸的晶体管，SSEDL 也能应对工艺变化。