The paradigm of Edge Computing in Internet of Things (IoT) demands high-throughput implementations of IoT edge devices. Security algorithms used in these devices heavily use GF(2^m) multiplications. Systolic structures for GF(2^m) multipliers can offer high throughput rates along with other features such as regularity, concurrency, and modularity. Many systolic architectures for GF(2^m) multiplier were proposed in the literature to achieve low area and time complexities. In this paper, we propose a high-throughput and low area-delay complexity systolic structure for the hardware realization of polynomial basis multiplication in GF(2^m) for a class of trinomials. The complexity analysis shows that the proposed architecture results in achieving high throughput and less area-delay complexity compared with the existing polynomial basis multipliers in the literature. When compared with the best available multipliers, the multiplier realized using the proposed architecture achieves throughput improvement by 42% and reduction in area-delay product by 7% for $m=409.$ Application specific integrated circuit (ASIC) implementations of the proposed multiplier and the best available multipliers confirm that the proposed multiplier outperforms the other multipliers. Hence, the proposed high-throughput area-delay-efficient multiplier can be employed in IoT edge devices.

物联网（IoT）中边缘计算的范式要求IoT边缘设备的高吞吐量实现。这些设备中使用的安全算法大量使用GF（2 ^m）乘法。GF（2 ^m）乘法器的收缩结构可以提供高吞吐率以及其他功能，例如规则性，并发性和模块化。文献中提出了许多用于GF（2 ^m）乘法器的收缩架构，以实现较低的面积和时间复杂度。本文针对GF（2 ^m）中多项式基乘法的硬件实现，提出了一种高吞吐量，低时延复杂度的脉动结构。），用于一类三项式。复杂度分析表明，与文献中现有的多项式基乘器相比，所提出的体系结构可实现高吞吐量，并减少面积延迟复杂度。与最佳可用乘法器相比，使用建议的体系结构实现的乘法器可将吞吐量提高42％，而面积延迟乘积减少7％。$米=409。$所提议的乘法器和最佳可用乘法器的专用集成电路（ASIC）实现确认，所提议的乘法器的性能优于其他乘法器。因此，可以在物联网边缘设备中采用提出的高吞吐量面积延迟效率乘法器。