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Design and implementation of higher order sigma delta modulator circuits using FPAA
Analog Integrated Circuits and Signal Processing ( IF 1.2 ) Pub Date : 2020-06-08 , DOI: 10.1007/s10470-020-01667-0
Daisy Deenrii Roel , Manoj Kumar

In this paper, the prototyping of 3rd order, 4th order, 5th order, and 6th order sigma-delta analog to digital converters (Σ∆ ADCs) has been presented. It summarily portrays the method implemented for configuration and reconfiguration of the proposed circuits by using Field Programmable Analog Array (FPAA). Their function was determined in the time domain at a constant 1 V supply voltages which is a sinewave input signal of 20 kHz frequency. The sampling frequency is fs = 4 MHz and the Oversampling ratio is OSR = 50 which yields a bandwidth of 40 kHz. Practical experimentation of the circuits was carried out using the AN221E04 FPAA device from Anadigm. Circuit realization of 3rd order, 4th order, 5th order, and 6th order sigma-delta analog to digital converters (Σ∆ ADCs) using FPAA are shown in figures. Also, sinusoidal input and output waveforms of implemented architectures are shown. A comparison of the proposed designed circuits with the various sigma-delta modulators published in the previous paper is also shown. The proposed sigma-delta modulators can be applied in the investigation and practical study of designing programmable analog devices and systems based on FPAA.



中文翻译:

使用FPAA的高阶Σ-Δ调制器电路的设计和实现

本文介绍了三阶,四阶,五阶和六阶sigma-delta模数转换器(Σ∆ ADC)的原型。它概述了通过使用现场可编程模拟阵列(FPAA)实现的用于配置和重新配置所建议电路的方法。它们的功能是在时域中以恒定的1 V电源电压确定的,该电源电压为20 kHz频率的正弦波输入信号。采样频率为fs = 4 MHz,过采样率为OSR = 50,产生40 kHz的带宽。使用Anadigm的AN221E04 FPAA器件对电路进行了实际实验。图中显示了使用FPAA的三阶,四阶,五阶和六阶sigma-delta模数转换器(Σ∆ ADC)的电路实现。也,显示了已实现架构的正弦输入和输出波形。还显示了建议的设计电路与先前论文中发布的各种sigma-delta调制器的比较。所提出的Σ-Δ调制器可用于基于FPAA的可编程模拟器件和系统设计的研究和实践研究。

更新日期:2020-06-08
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