This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.

中文翻译：

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有线通信：数据传输的骨干

本文回顾了到2020年代无线连接数十亿个传感器节点的背景下对高性能有线通信的需求。它比较了最先进的有线收发器的性能，并强调了在CMOS技术缩放逐渐变窄的过程中提高性能的挑战。本文详细阐述了正在进行的研究，以跟踪具有可承受功耗预算的处理平台中不断增长的带宽需求。讨论了用于多通道接收器中的时钟恢复，数字CDR中的接收器前端，可重配置电压模式发送器以及全双工收发器中的PAM4均衡器的节能设计技术。