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A 0.5-to-3.5-GHz Full-Duplex Mixer-First Receiver With Cartesian Synthesized Self-Interference Suppression Interface in 65-nm CMOS
IEEE Transactions on Microwave Theory and Techniques ( IF 4.3 ) Pub Date : 2020-06-01 , DOI: 10.1109/tmtt.2020.2989386
Ali Ershadi , Kamran Entesari

This article presents a wideband self-interference (SI) canceling full-duplex (FD) receiver. In-band linearity requirement for an FD receiver is studied. It is shown that an FD receiver requires a minimum IB-IIP3 which if not provided, results in sensitivity degradation. To provide the required out-of-band linearity, an eight-phase passive mixer-first architecture is chosen for the receiver. In order to achieve SI cancellation, quadrature components from TX replica are created, their magnitudes are scaled, and the approximated SI is injected to the receiver. The cancellation occurs after downconversion, in an RF to baseband (BB) cancellation domain. As a proof of concept, a prototype is fabricated and measured in a 65-nm CMOS process. More than 35-dB cancellation is measured for 10-MHz bandwidth (BW) 64-QAM modulated signals in a single RF downconverted domain. The noise figure (NF) in half-duplex (HD) and FD mode is 3.3 and 5.3 dB, respectively, with only 2-dB degradation for switching from HD to FD. The receiver has adjustable 30-to-50-dB conversion gain, consumes 20–58-mW power, and achieves IB-IIP3 of +6 dBm. The cancellation path achieves more than 35-dBm IIP3.

中文翻译:

在 65-nm CMOS 中具有笛卡尔合成自干扰抑制接口的 0.5 至 3.5-GHz 全双工混频器优先接收器

本文介绍了一种宽带自干扰 (SI) 消除全双工 (FD) 接收器。研究了 FD 接收器的带内线性度要求。结果表明,FD 接收器需要最小的 IB-IIP3,如果不提供,则会导致灵敏度下降。为了提供所需的带外线性度,为接收器选择了八相无源混频器优先架构。为了实现 SI 消除,创建来自 TX 副本的正交分量,缩放它们的幅度,并将近似的 SI 注入接收器。消除发生在下变频之后,在 RF 到基带 (BB) 消除域中。作为概念验证,原型是在 65 纳米 CMOS 工艺中制造和测量的。在单个 RF 下变频域中,针对 10 MHz 带宽 (BW) 64-QAM 调制信号测量了超过 35 dB 的消除。半双工 (HD) 和 FD 模式下的噪声系数 (NF) 分别为 3.3 和 5.3 dB,从 HD 切换到 FD 仅降低 2 dB。接收器具有 30-50-dB 的可调转换增益,消耗 20-58-mW 功率,并实现 +6dBm 的 IB-IIP3。消除路径达到超过 35-dBm IIP3。
更新日期:2020-06-01
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