A review is presented of the key techniques for high-power, high-efficiency millimeter-Wave (mm-Wave) 5G power amplifier (PA) design in deep submicrometer planar and FinFET bulk CMOS processes. The work utilizes a distributed unit cell-based layout technique for neutralized differential pairs and stacking transistors in bulk CMOS. This article also proposes a prediction of saturated output power ( ${\mathrm {P}}_{{\mathrm {sat}}}$ ) and its corresponding maximized power-added efficiency (PAE) at 39 GHz for three candidate power combined architectures of three-stage PAs with two supporting prototype PAs fabricated in 16-nm FinFET and 28-nm planar bulk CMOS processes. The single-stage two-stack 16-nm FinFET PA generates a ${\mathrm {P}}_{{\mathrm {sat}}}$ of 18.3 dBm from a 1.8-V supply at 39 GHz with a drain efficiency (DE) of 35.5%. The three-stage 28-nm PA incorporates a two-stack output stage with a balanced and compact 4-to-1 series-parallel combiner and achieves a ${\mathrm {P}}_{{\mathrm {sat}}}$ of 26 dBm using a 2.2-V supply, PAE of 26.6%, and high average power measurements with single-carrier and 5G new radio orthogonal frequency-division multiplexing modulations with competitive efficiencies. Long-term reliability measurements are performed using aging acceleration techniques to demonstrate the robustness of both prototypes. The competitive power and efficiency results, supported with reliability measurements, show that bulk CMOS can achieve performance comparable to SOI CMOS for generating high power at mm-Wave frequencies.

中文翻译：

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深亚微米平面和 FinFET 体 CMOS 中毫米波 5G 功率放大器的高功率生成

综述了深亚微米平面和 FinFET 体 CMOS 工艺中高功率、高效率毫米波 (mm-Wave) 5G 功率放大器 (PA) 设计的关键技术。这项工作利用基于分布式单位单元的布局技术，用于中和差分对和体 CMOS 中的堆叠晶体管。本文还提出了饱和输出功率的预测（ ${\mathrm {P}}_{{\mathrm {sat}}}$ ) 及其相应的最大功率附加效率 (PAE) 在 39 GHz 下，用于三级 PA 的三个候选功率组合架构，其中两个支持原型 PA 以 16-nm FinFET 和 28-nm 平面体 CMOS 工艺制造。单级两叠 16 纳米 FinFET PA 产生 ${\mathrm {P}}_{{\mathrm {sat}}}$ 18.3 dBm 来自 39 GHz 的 1.8 V 电源，漏极效率 (DE) 为 35.5%。三级 28-nm PA 包含一个带有平衡且紧凑的 4 对 1 串并联组合器的两堆栈输出级，并实现了 ${\mathrm {P}}_{{\mathrm {sat}}}$ 26 dBm 使用 2.2-V 电源、26.6% 的 PAE 和高平均功率测量，使用具有竞争力的效率的单载波和 5G 新无线电正交频分复用调制。使用老化加速技术进行长期可靠性测量，以证明两种原型的稳健性。在可靠性测量的支持下，具有竞争力的功率和效率结果表明，体 CMOS 可以实现与 SOI CMOS 相当的性能，以在毫米波频率下产生高功率。