This article presents an 8T static random access memory (SRAM) macro with vertical read wordline (RWL) and selective dual split power (SDSP) lines techniques. The proposed vertical RWL reduces dynamic energy consumption during read operation by charging and discharging only selected read bitlines (RBLs). The data-aware SDSP technique combined with vertical write bitlines enhances both the write margin (WM) and the static noise margin (SNM). A 16-kb SRAM test chip fabricated in 65-nm CMOS technology demonstrates the minimum energy consumption of 0.506 pJ at 0.4 V and the minimum operating voltage of 0.26 V.

中文翻译：

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具有垂直读取字线和选择性双分离电源线的 0.506-pJ 16-kb 8T SRAM

本文介绍了具有垂直读取字线 (RWL) 和选择性双分离电源 (SDSP) 线技术的 8T 静态随机存取存储器 (SRAM) 宏。所提出的垂直 RWL 通过仅​​对选定的读取位线 (RBL) 进行充电和放电来降低读取操作期间的动态能耗。数据感知 SDSP 技术与垂直写入位线相结合，提高了写入裕度 (WM) 和静态噪声裕度 (SNM)。采用 65-nm CMOS 技术制造的 16-kb SRAM 测试芯片表明，0.4 V 时的最低能耗为 0.506 pJ，最低工作电压为 0.26 V。