Design methodology for ultrahigh-speed 5-2 and 7-2 compressors has been illustrated in this article. With the help of introduced procedure, the gate-level delay has been reduced considerably when compared with the previous designs, while the total transistor and gate count remain in a reasonable range. By starting the discussion for the carry rippling problem in n - 2 compressors, the method has been developed for 5-2 compressor and is expanded for 7-2 architecture, which shows 32% and 30% improvement in speed performance for these structures, respectively. Also, the careful design considerations have been taken into account to keep other characteristics, such as power and active, are at a reasonable level. Moreover, for a fair comparative conclusion, the best-reported circuits have been redesigned, and their parasitic elements were extracted utilizing the same technology employed for the synthesis of the proposed circuits. Finally, a typical 16 × 16 bit multiplier has been implemented to investigate the efficiency of the designed compressor blocks. Based on the postlayout simulation results provided using HSPICE for TSMC 0.18-μm standard CMOS technology and 1.8-V power supply, the proposed compressors demonstrate better speed performance and power-delay product (PDP) factor over previous works. As the results depict, the delay of 303 ps has been achieved for the 5-2 compressor while the measured delay of the designed 7-2 compressor is 464 ps.

中文翻译：

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采用 CMOS 工艺的超快速高性能 5-2 和 7-2 压缩机，可实现快速并行累加


本文阐述了超高速 5-2 和 7-2 压缩机的设计方法。借助所引入的流程，与以前的设计相比，门级延迟已大大减少，而总晶体管和门数仍保持在合理的范围内。通过开始讨论 n - 2 压缩机中的进位纹波问题，该方法已针对 5-2 压缩机进行了开发，并针对 7-2 架构进行了扩展，这表明这些结构的速度性能分别提高了 32% 和 30% 。此外，还考虑了仔细的设计考虑，以将其他特性（例如功率和活动）保持在合理的水平。此外，为了获得公平的比较结论，报告的最佳电路已经过重新设计，并且利用与所提出的电路的合成所采用的相同技术来提取它们的寄生元件。最后，实现了一个典型的 16 × 16 位乘法器来研究所设计的压缩器模块的效率。基于使用 TSMC 0.18μm 标准 CMOS 技术和 1.8V 电源的 HSPICE 提供的布局后仿真结果，所提出的压缩机比以前的工作表现出更好的速度性能和功率延迟乘积 (PDP) 因数。如结果所示，5-2 压缩器实现了 303 ps 的延迟，而设计的 7-2 压缩器的测量延迟为 464 ps。