Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In this article, a high-speed, low-power 10-T XOR-XNOR circuit is proposed, which provides full swing outputs simultaneously with improved delay performance. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. The proposed circuit reduces the power delay product (PDP) at least by 7.5% than that of the available XOR-XNOR modules. Four different designs of FAs are also proposed in this article utilizing the proposed XOR-XNOR circuit and available sum and carry modules. The proposed FAs provide 2%-28.13% improvement in terms of PDP than that of other architectures. To measure the driving capabilities, the proposed FAs are embedded in 2-, 4-, and 8-bit cascaded full adder (CFA) structures. Results show that two of the proposed FAs provide the best performance for a higher number of bits among all the FAs.

中文翻译：

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使用高性能 10-T XOR、NOR 单元的高速混合逻辑全加器


混合逻辑风格广泛用于实现全加器 (FA) 电路。混合FA在延迟、功耗和驱动能力方面的性能很大程度上取决于XOR-XNOR电路的性能。在本文中，提出了一种高速、低功耗的 10-T XOR-XNOR 电路，该电路可同时提供全摆幅输出和改进的延迟性能。所提出电路的性能是通过使用 90 nm CMOS 技术在 cadence virtuoso 环境中进行仿真来测量的。与现有 XOR-XNOR 模块相比，所提议的电路将功率延迟积 (PDP) 至少降低了 7.5%。本文还利用所提出的 XOR-XNOR 电路以及可用的求和和进位模块提出了四种不同的 FA 设计。与其他架构相比，所提出的 FA 在 PDP 方面提供了 2%-28.13% 的改进。为了测量驱动能力，所提出的 FA 被嵌入到 2 位、4 位和 8 位级联全加器 (CFA) 结构中。结果表明，在所有 FA 中，所提出的两个 FA 在位数较多时提供了最佳性能。