Carbon-nanotube FETs (CNFETs) are potential successors to CMOS transistors; these emerging devices have a low intrinsic delay due to near-ballistic transport in carbon nanotubes (CNTs). As CNFETs are evaluated for circuit/system design, it is important to analyze variations in CNT process parameters. In this article, we present a systematic approach to quantify the impact of these imperfections on the transistor- and gate-level performances of CNT-based circuits. Process variations are investigated to identify the critical device parameters that have maximum impact on the device on-current. We also present a model that predicts the realistic CNFET yield in the presence of process variations. Finally, the impact of manufacturing defects, such as pinholes in the gate dielectric and parasitic CNFETs formed due to imperfect etching, are modeled and evaluated using HSPICE.

中文翻译：

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工艺变化和制造缺陷对碳纳米管 FET 性能的影响分析

碳纳米管 FET (CNFET) 是 CMOS 晶体管的潜在继承者；由于碳纳米管 (CNT) 中的近弹道传输，这些新兴器件具有较低的固有延迟。由于 CNFET 是针对电路/系统设计进行评估的，因此分析 CNT 工艺参数的变化非常重要。在本文中，我们提出了一种系统方法来量化这些缺陷对基于 CNT 的电路的晶体管级和栅极级性能的影响。研究工艺变化以识别对器件导通电流影响最大的关键器件参数。我们还提出了一个模型，该模型可以在存在工艺变化的情况下预测实际的 CNFET 良率。最后，制造缺陷的影响，例如栅极电介质中的针孔和由于蚀刻不完善而形成的寄生 CNFET，