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Heterogeneous 3D Integration for a RISC-V System with STT-MRAM
IEEE Computer Architecture Letters ( IF 1.4 ) Pub Date : 2020-01-01 , DOI: 10.1109/lca.2020.2992644
Lingjun Zhu , Lennart Bamberg , Anthony Agnesina , Francky Catthoor , Dragomir Milojevic , Manu Komalan , Julien Ryckaert , Alberto Garcia-Ortiz , Sung Kyu Lim

Spin Torque Transfer Magnetic RAM (STT-MRAM) is a promising Non-Volatile Memory (NVM) technology achieving high density, low leakage power, and relatively small read/write delays. It provides a solution to improve the performance and to mitigate the leakage power consumption compared to SRAM-based processors. However, the process heterogeneity and the sophisticated back-end-of-line (BEOL) structure make it difficult to integrate the STT-MRAM in two-dimensional integrated circuits (2D ICs). In this article, we implement a RISC-V-based processor with STT-MRAM using a heterogeneous 3D integration methodology. Compared with the SRAM-based 2D counterpart, the MRAM-based 3D IC provides up to 17.55 percent silicon area saving, together with either 34.74 percent performance gain or 13.90 percent energy reduction.

中文翻译:

具有 STT-MRAM 的 RISC-V 系统的异构 3D 集成

自旋扭矩转移磁性 RAM (STT-MRAM) 是一种很有前途的非易失性存储器 (NVM) 技术,可实现高密度、低泄漏功率和相对较小的读/写延迟。与基于 SRAM 的处理器相比,它提供了一种提高性能和降低泄漏功耗的解决方案。然而,工艺异质性和复杂的后端 (BEOL) 结构使得很难将 STT-MRAM 集成到二维集成电路 (2D IC) 中。在本文中,我们使用异构 3D 集成方法实现了基于 RISC-V 的处理器和 STT-MRAM。与基于 SRAM 的 2D 芯片相比,基于 MRAM 的 3D IC 可节省高达 17.55% 的硅面积,同时性能提升 34.74% 或能耗降低 13.90%。
更新日期:2020-01-01
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