Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core GPUs, and programmable FPGAs. The effective utilization of these architectures poses several challenges, among which a primary one is power consumption. Voltage reduction is one of the most efficient methods to reduce power consumption of a chip. With the galloping adoption of hardware accelerators (i.e., GPUs and FPGAs) in large datacenters and other large-scale computing infrastructures, a comprehensive evaluation of the safe voltage reduction levels for each different chip can be employed for efficient reduction of the total power. We present a survey of recent studies in voltage margins reduction at the system level for modern CPUs, GPUs and FPGAs. The pessimistic voltage guardbands inserted by the silicon vendors can be exploited in all devices for significant power savings. On average, voltage reduction can reach 12% in multicore CPUs, 20% in manycore GPUs and 39% in FPGAs.

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超越保守极限：现代硬件利润的综合分析

现代大规模计算系统（数据中心、超级计算机、云和边缘设置以及高端网络物理系统）采用由多核 CPU、通用多核 GPU 和可编程 FPGA 组成的异构架构。这些架构的有效利用带来了几个挑战，其中一个主要挑战是功耗。降压是降低芯片功耗最有效的方法之一。随着硬件加速器（即GPU和FPGA）在大型数据中心和其他大规模计算基础设施中的迅速采用，可以综合评估每个不同芯片的安全降压水平，以有效降低总功耗。我们对现代 CPU、GPU 和 FPGA 的系统级电压裕度降低的最新研究进行了调查。硅供应商插入的悲观电压保护带可用于所有设备，以显着节省功耗。平均而言，多核 CPU 的电压降低可达 12%，多核 GPU 的电压降低可达 20%，FPGA 的电压降低 39%。