Many engineering and scientific applications require high precision arithmetic. IEEE 754-2008 compliant (floating-point) arithmetic is the de facto standard for performing these computations. Recently, posit arithmetic has been proposed as a drop-in replacement for floating-point arithmetic. The posit data representation and arithmetic offer several absolute advantages over the floating-point format and arithmetic including higher dynamic range, better accuracy, and superior performance-area trade-offs. In this paper, we present a consolidated general-purpose processor-based framework to support posit arithmetic empiricism. The end-users of the framework have the liberty to seamlessly experiment with their applications using posit and floating-point arithmetic since the framework is designed for the two number systems to coexist. The framework consists of Melodica and Clarinet. Melodica is a posit arithmetic core that implements parametric fused-multiply-accumulate and, more importantly, supports the quire data type. Clarinet is a Melodica-enabled processor based on the RISC-V ISA. To the best of our knowledge, this is the first-ever integration of quire to a RISC-V core. To show the effectiveness of the Clarinet platform, we perform an extensive application study and benchmarking on some of the common linear algebra and computer vision kernels. We perform ASIC synthesis of Clarinet and Melodica on a 90 nm-CMOS Faraday process. Finally, based on our analysis and synthesis results, we define a quality metric for the different instances of Clarinet that gives us initial recommendations on the goodness of the instances. Clarinet-Melodica is an easy-to-experiment platform that will be made available in open-source for posit arithmetic empiricism.

中文翻译：

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CLARINET：基于 RISC-V 的实证算术经验主义框架

许多工程和科学应用需要高精度算术。IEEE 754-2008 兼容（浮点）算法是执行这些计算的事实上的标准。最近，已提出 posit 算术作为浮点算术的直接替代品。与浮点格式和算术相比，位置数据表示和算术提供了几个绝对优势，包括更高的动态范围、更高的精度和卓越的性能-面积权衡。在本文中，我们提出了一个统一的基于通用处理器的框架来支持实证算术经验主义。该框架的最终用户可以自由地使用 posit 和浮点算法无缝地试验他们的应用程序，因为该框架是为两个数字系统共存而设计的。该框架由 Melodica 和 Clarinet 组成。Melodica 是一个 posit 算术核心，它实现了参数化 fused-multiply-accumulate，更重要的是，它支持 quire 数据类型。Clarinet 是基于 RISC-V ISA 的支持 Melodica 的处理器。据我们所知，这是有史以来第一次将 quire 集成到 RISC-V 内核。为了展示 Clarinet 平台的有效性，我们对一些常见的线性代数和计算机视觉内核进行了广泛的应用研究和基准测试。我们在 90 nm-CMOS Faraday 工艺上执行 Clarinet 和 Melodica 的 ASIC 合成。最后，根据我们的分析和综合结果，我们为 Clarinet 的不同实例定义了一个质量指标，它为我们提供了关于实例优劣的初步建议。