The frequency bands below 3 GHz are occupied by various wireless applications. The overcrowding of many applications in these bands is the primary source of distortion in the wireless system. To combat distortion in the system, the radio frequency (RF) blocks must satisfy the linearity requirements of the application. Hence, in this paper, a high linear wideband low noise amplifier (LNA) stage is proposed for RF front-end. The LNA uses the combination of common-gate (CG) and common-source (CS) stages for cancelling the noise and distortion of the input matching CG stage. The CS stage exploits complementary derivative superposition (CDS) for linearity improvement, and cross-coupled local feedback network is employed for noise cancellation at the output. The LNA stage is designed using UMC 180 nm CMOS process technology and post-layout characterizations are carried out using Cadence SpectreRF circuit simulator. Also, the process corner, voltage, and temperature (PVT) variation analysis and Monte-Carlo simulations for mismatch analysis are carried out to verify the reliability of the LNA. The designed LNA has an input referred third-order intercept point (IIP3) of 8.85 dBm. The proposed LNA has a maximum gain of 23.96 dB and minimum noise figure (NF) of 1.4 dB with a total current consumption of 3.1 mA from a 1.8 V supply.

3 GHz以下的频带被各种无线应用占用。这些频段中许多应用的过度拥挤是无线系统失真的主要根源。为了消除系统中的失真，射频（RF）模块必须满足应用的线性要求。因此，在本文中，提出了一种用于射频前端的高线性宽带低噪声放大器（LNA）级。LNA使用共栅（CG）和共源（CS）级的组合来消除输入匹配CG级的噪声和失真。CS级利用互补导数叠加（CDS）来改善线性度，并采用交叉耦合的本地反馈网络来消除输出端的噪声。LNA平台是使用UMC 180 nm CMOS工艺技术设计的，而布局后的表征则使用Cadence SpectreRF电路模拟器进行。此外，还进行了工艺拐角，电压和温度（PVT）变化分析以及失配分析的蒙特卡洛仿真，以验证LNA的可靠性。设计的LNA具有8.85 dBm的输入参考三阶交调点（IIP3）。拟议的LNA的最大增益为23.96 dB，最小噪声系数（NF）为1.4 dB，1.8 V电源的总电流消耗为3.1 mA。设计的LNA具有8.85 dBm的输入参考三阶交调点（IIP3）。拟议的LNA的最大增益为23.96 dB，最小噪声系数（NF）为1.4 dB，1.8 V电源的总电流消耗为3.1 mA。设计的LNA具有8.85 dBm的输入参考三阶交调点（IIP3）。拟议的LNA的最大增益为23.96 dB，最小噪声系数（NF）为1.4 dB，1.8 V电源的总电流消耗为3.1 mA。