We describe the implementation of Boosted Decision Trees in the hls4ml library, which allows the translation of a trained model into FPGA firmware through an automated conversion process. Thanks to its fully on-chip implementation, hls4ml performs inference of Boosted Decision Tree models with extremely low latency. With a typical latency less than 100 ns, this solution is suitable for FPGA-based real-time processing, such as in the Level-1 Trigger system of a collider experiment. These developments open up prospects for physicists to deploy BDTs in FPGAs for identifying the origin of jets, better reconstructing the energies of muons, and enabling better selection of rare signal processes.

中文翻译：

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用于粒子物理的 FPGA 中增强决策树的快速推理

我们描述了 hls4ml 库中提升决策树的实现，它允许通过自动转换过程将训练模型转换为 FPGA 固件。由于其完全片上实现，hls4ml 以极低的延迟执行提升决策树模型的推理。该解决方案的典型延迟小于 100 ns，适用于基于 FPGA 的实时处理，例如在对撞机实验的 Level-1 Trigger 系统中。这些发展为物理学家在 FPGA 中部署 BDT 以识别喷流的起源、更好地重建 μ 子的能量以及更好地选择稀有信号过程开辟了前景。