Despite the ability of type-3 phase-locked loop (PLL) to provide zero steady-state error when a three-phase voltage experiences frequency ramp change, its major drawback is slow dynamic performance and instability during voltage sag condition. In this paper, by obtaining the linearised model of PLL, instability associated with the presence of voltage amplitude within the PLL control loop is illustrated. Furthermore, analysis of two common techniques employed in improving PLL stability (high phase margin design and use of phase-lead compensator) is presented and their inapplicability to three-phase type-3 PLL is revealed. Thus, to address the said problems, a gain compensation technique is proposed in this paper. In the proposed approach, the PLL loop gain is adjusted by inserting a DC gain within the PLL control loop when the frequency of supply voltage deviates from its nominal value. The inserted DC gain compensates for reduction in voltage amplitude within the PLL control loop, thus, enhancing PLL's stability especially during voltage sags. Also, the gain increases PLL's bandwidth thereby improving its estimation speed. Effectiveness of the proposed solution is confirmed through experimental studies and it is compared with five existing type-3 PLL schemes and a type-2 PLL.

中文翻译：

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增益补偿方法可改善三相3型PLL的低压穿越和动态性能

尽管当三相电压经历频率斜坡变化时，类型3锁相环（PLL）能够提供零稳态误差，但其主要缺点是动态性能较慢，并且在电压骤降条件下不稳定。在本文中，通过获得PLL的线性化模型，可以说明与PLL控制回路内电压幅度的存在有关的不稳定性。此外，分析了两种用于提高PLL稳定性的常用技术（高相位裕度设计和使用相位超前补偿器），并揭示了它们不适用于三相3型PLL。因此，为了解决上述问题，本文提出了一种增益补偿技术。在建议的方法中，当电源电压的频率偏离其标称值时，可通过在PLL控制环路中插入一个直流增益来调节PLL环路增益。插入的DC增益补偿了PLL控制环路内电压幅度的减小，从而增强了PLL的稳定性，尤其是在电压骤降期间。同样，增益增加了PLL的带宽，从而提高了其估计速度。通过实验研究证实了所提出解决方案的有效性，并将其与五个现有的3型PLL方案和2型PLL进行了比较。