This paper presents a 12-bit 2.4 GS/s analog-to-digital converter (ADC) employing four time-interleaved (TI) pipelined channels with a novel on-chip timing mismatch calibration in 40 nm CMOS process. TI architecture can increase the effective sampling rate of ADC but the dynamic performance of TI-ADC system is seriously degraded by offset, gain, and timing mismatches among the channels. Timing mismatch is the most challenging barrier among these mismatches due to the difficulty and complexity of its detection and correction. An automatic wideband timing mismatch detection algorithm is proposed for achieving a wide frequency range of timing mismatch detection without complex calculations. By adopting the proposed mismatch-free variable delay line (VDL), the full-scale traversal timing mismatch correction accomplishes an accurate result without missing codes. Measurement results show that the spurious free dynamic range (SFDR) of the prototype ADC is improved from 55.2 dB to 72.8 dB after calibration at 2.4 GS/s with a 141 MHz input signal. It can achieve an SFDR above 60 dB across the entire first Nyquist band based on the timing mismatch calibration and retiming technology. The prototype ADC chip occupies an area of 3 mm × 3 mm and it consumes 420 mW from a 1.8 V supply.

中文翻译：

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具有新型片上时序失配校准功能的12位2.4 GS / s四通道流水线ADC

本文介绍了一种12位2.4 GS / s模数转换器（ADC），它采用四个时间交错（TI）流水线通道，并在40 nm CMOS工艺中采用了新颖的片上时序失配校准。TI架构可以提高ADC的有效采样率，但是TI-ADC系统的动态性能会因通道之间的失调，增益和时序失配而严重降低。由于其检测和校正的难度和复杂性，时序不匹配是这些不匹配中最具挑战性的障碍。提出了一种自动宽带定时失配检测算法，以实现宽范围的定时失配检测频率范围，而无需进行复杂的计算。通过采用建议的无失配可变延迟线（VDL），满量程遍历时序失配校正可实现准确的结果而不会丢失代码。测量结果表明，在以141 MHz输入信号进行2.4 GS / s校准后，原型ADC的无杂散动态范围（SFDR）从55.2 dB提高到72.8 dB。基于时序失配校准和重定时技术，它可以在整个第一奈奎斯特频带上实现60 dB以上的SFDR。原型ADC芯片占地3 mm×3 mm，从1.8 V电源消耗的功率为420 mW。基于时序失配校准和重定时技术，它可以在整个第一奈奎斯特频带上实现60 dB以上的SFDR。原型ADC芯片占地3 mm×3 mm，从1.8 V电源消耗的功率为420 mW。基于时序失配校准和重定时技术，它可以在整个第一奈奎斯特频带上实现60 dB以上的SFDR。原型ADC芯片占地3 mm×3 mm，从1.8 V电源消耗的功率为420 mW。