In this paper, a new scheme of logic function realization in dynamic positive feedback source-coupled logic (D-PFSCL) style is proposed. The existing scheme implements only NOR/OR based realization of a logic function. Thus, a complex function in D-PFSCL has high gate count which degrades the overall circuit performance measured in terms of power and delay. This paper therefore aims to resolve the issue by proposing a scheme which modifies the structure of a D-PFSCL gate. The modified gate exhibits AND/OR functionality and is used to realize various functions. Simulations have been carried out by implementing various functions and comparing their performance with the existing schemes at 1 GHz. The results of performance comparison with existing schemes indicates significant reuduction in gate count resulting in overall performance improvement.

本文提出了一种动态正反馈源耦合逻辑（D-PFSCL）形式的逻辑功能实现新方案。现有方案仅实现基于NOR / OR的逻辑功能的实现。因此，D-PFSCL中的复杂功能具有高门数，从而降低了在功率和延迟方面测得的整体电路性能。因此，本文旨在通过提出一种修改D-PFSCL门结构的方案来解决该问题。修改后的门具有AND / OR功能，可用于实现各种功能。通过实现各种功能并将其性能与1 GHz下的现有方案进行比较来进行仿真。与现有方案进行性能比较的结果表明，门数显着减少，从而改善了总体性能。