The impacts of aging and process variations on the performance of VLSI systems is increasing with each process generation. The conventional way to counteract them are extensive guard bands, which are calculated at system design time. Hence, they are necessarily worst case guard bands, i.e., most often too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement based adaptive voltage scaling (AVS). The performance measurement is typically determined by means of dedicated sensors or canary logic. The parametrization of such AVS systems relies on assumptions regarding the relative behavior of the sensor and the application logic. Most published approaches use manually gained empirical data for this purpose. However, an automatic calibration procedure is needed for the practical application of these approaches. We propose such an automated calibration procedure and evaluate it on multiple FPGAs to consider the effects of aging and process variation. Furthermore, we use two designs to cover leakage power and dynamic power dominated scenarios. We achieve average power savings of 67% for a leakage dominated design and 48% for a test case with dominant dynamic power. Furthermore, we investigate the limitations of AVS systems regarding their capability to counteract fast disturbances, e.g., voltage drop.

随着每一代工艺的发展，老化和工艺变化对VLSI系统性能的影响越来越大。抵消它们的常规方法是扩展保护带，这些保护带是在系统设计时计算出的。因此，它们必然是最坏情况的保护带，即，大多数情况下过于悲观。当前的研究试图通过基于自适应电压缩放（AVS）的现场性能测量来缓解这种情况。通常通过专用传感器或Canary逻辑确定性能度量。这种AVS系统的参数化取决于关于传感器和应用逻辑的相对行为的假设。为此，大多数已发布的方法都使用人工获得的经验数据。但是，这些方法的实际应用需要自动校准程序。我们提出了这种自动校准程序，并在多个FPGA上对其进行评估，以考虑老化和工艺变化的影响。此外，我们使用两种设计来涵盖泄漏功率和动态功率为主的场景。对于以泄漏为主导的设计，我们平均节省了67％的功率，而对于动态功率占优势的测试用例，则平均节省了48％。此外，我们研究了AVS系统在抵抗快速干扰（例如电压降）方面的局限性。