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SOI Schottky Barrier Nanowire MOSFET with Reduced Ambipolarity and Enhanced Electrostatic Integrity
Journal of Electronic Materials ( IF 2.1 ) Pub Date : 2020-05-13 , DOI: 10.1007/s11664-020-08164-0
Amit Saxena , Manoj Kumar , R. K. Sharma , R. S. Gupta

The proposed silicon-on-insulator Schottky barrier (SOI-SB) nanowire metal–oxide–semiconductor field-effect transistor (NW-MOSFET) is extensively investigated to further improve its analog/radiofrequency (RF) performance. The proposed device shows effectively improved electrostatic control and a reduced ambipolar effect in the OFF-state current. Simulations of the proposed device are conducted and compared with a dielectric pocket Schottky barrier NW-MOSFET for a channel length of 22 nm and radius 5 nm. The SOI-SB NW-MOSFET shows improved performance in terms of IOFF current, ION/IOFF ratio, subthreshold slope, early voltage, transconduction generation factor, and intrinsic gain.



中文翻译:

降低双极性和增强静电完整性的SOI肖特基势垒纳米线MOSFET

提议的绝缘体上硅肖特基势垒(SOI-SB)纳米线金属氧化物半导体场效应晶体管(NW-MOSFET)进行了广泛研究,以进一步改善其模拟/射频(RF)性能。所提出的器件在截止状态电流中显示出有效改善的静电控制和降低的双极性效应。进行了拟议器件的仿真,并与沟道长度为22 nm,半径为5 nm的电介质袋肖特基势垒NW-MOSFET进行了比较。SOI-SB NW-MOSFET在I OFF电流,I ON / I OFF比,亚阈值斜率,早期电压,跨导生成因子和本征增益方面表现出更高的性能。

更新日期:2020-05-13
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