In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chips (408x DDR3, 652x DDR4, and 520x LPDDR4) from 300 DRAM modules (60x DDR3, 110x DDR4, and 130x LPDDR4) with RowHammer protection mechanisms disabled, spanning multiple different technology nodes from across each of the three major DRAM manufacturers. Our studies definitively show that newer DRAM chips are more vulnerable to RowHammer: as device feature size reduces, the number of activations needed to induce a RowHammer bit flip also reduces, to as few as 9.6k (4.8k to two rows each) in the most vulnerable chip we tested. We evaluate five state-of-the-art RowHammer mitigation mechanisms using cycle-accurate simulation in the context of real data taken from our chips to study how the mitigation mechanisms scale with chip vulnerability. We find that existing mechanisms either are not scalable or suffer from prohibitively large performance overheads in projected future devices given our observed trends of RowHammer vulnerability. Thus, it is critical to research more effective solutions to RowHammer.

中文翻译：

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重新审视 RowHammer：现代 DRAM 设备和缓解技术的实验分析

为了更多地了解 RowHammer 如何在电路级影响现代和未来设备，我们首先展示了 RowHammer 在来自 300 个 DRAM 模块（60x DDR3 、110x DDR4 和 130x LPDDR4)，禁用 RowHammer 保护机制，跨越三大 DRAM 制造商中的每一个的多个不同技术节点。我们的研究明确表明，较新的 DRAM 芯片更容易受到 RowHammer 的影响：随着设备特征尺寸的减小，引发 RowHammer 位翻转所需的激活次数也减少到 9.6k（每行 4.8k 到两行）我们测试过的最脆弱的芯片。我们在从我们的芯片中获取的真实数据的背景下使用周期精确模拟评估了五种最先进的 RowHammer 缓解机制，以研究缓解机制如何随着芯片漏洞而扩展。我们发现，鉴于我们观察到的 RowHammer 漏洞趋势，现有机制要么不可扩展，要么在预计的未来设备中遭受过高的性能开销。因此，研究更有效的 RowHammer 解决方案至关重要。