Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)–based DSPs, scaling represents a performance bottleneck based on the complexity of inter‐modulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well‐known moduli sets {2ⁿ − 1, 2ⁿ, 2ⁿ + 1} and {2ⁿ, 2ⁿ − 1, 2ⁿ⁺¹ − 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic‐friendly moduli set {2^n+p, 2ⁿ − 1, 2ⁿ⁺¹ − 1}. The proposed algorithm yields high speed and energy‐efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed‐radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler.

中文翻译：

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用于三模数集{2n + p，2n − 1，2n + 1 − 1}的高效可编程的2幂次缩放器

由于数字信号处理器（DSP）中算术过程的迭代性质，定标是一项重要的操作。在基于残数系统（RNS）的DSP中，缩放比例代表了模间运算复杂性的性能瓶颈。设计一个高效RNS缩放器用于特定模数集，文献的主体一直致力于公知的模量集{2的研究^Ñ  - 1，2 ^Ñ，2 ^Ñ  + 1}和{2 ^Ñ，2 ^Ñ  - 1，2 ^{n +}  1-1}，及其垂直或水平形式的扩展。在这项研究中，我们为算术友好模集{2 ^{n + p}，2ⁿ  − 1，2 ^{n +}  1-1}。基于对混合基数表示，并行性和硬件共享技术的有效利用，所提出的算法可实现RNS可编程缩放器的高速高效节能实现。对于相同的模数集，与唯一可用的高效混合可编程缩放器相比，针对130 nm CMOS ASIC技术获得的实验结果证明了所提出的可编程缩放器的优越性。与混合可编程定标器相比，建议的定标器可减少43.28％的功耗，33.27％的执行速度，并平均节省28.55％的面积。