当前位置: X-MOL 学术Opt. Quant. Electron. › 论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
An investigation on the cascaded operation of photonic crystal based all optical logic gates and verification of De Morgan’s law
Optical and Quantum Electronics ( IF 3.3 ) Pub Date : 2020-05-27 , DOI: 10.1007/s11082-020-02384-8
E. G. Anagha , R. K. Jeyachitra

In this paper, a new set of configurations are proposed to implement simple and highly compact photonic crystal based all-optical logic AND and OR gates. These newly designed logic gates operate at the telecommunication wavelength of 1550 nm and consume very low power compared to the existing designs. The basic all-optical logic gates are cascaded to operate as the universal gates NAND and NOR. The various parameters such as response time, contrast ratio and footprint are analyzed and optimized based on structure parameters such as radius and lattice constant. The proposed structures have very low power consumption in the range of 1 $$\upmu$$ μ W with a footprint of 168 $$\upmu \mathrm{m}^2$$ μ m 2 for the AND gate and 150 $$\upmu \mathrm{m}^2$$ μ m 2 for the OR gate respectively. The value of contrast ratio for the proposed AND gate is 8.45 dB. The response time for OR gate is 0.4 ps and that of AND gate is 0.16 ps resulting in bitrates up to 6.25 Tbps. The contrast ratio obtained for the cascaded operation of NAND and NOR gates are 5.29 dB and 5.3 dB respectively. The band gap diagram for the proposed gates are attained using Plane Wave Expansion method and their performance is studied using Finite Difference Time Domain technique. Further, the realization of De Morgan’s law is achieved by cascading the proposed all-optical logic gates and hence verifying the truth tables for the same.

中文翻译:

基于全光逻辑门的光子晶体级联运行研究及德摩根定律验证

在本文中,提出了一组新的配置来实现简单且高度紧凑的基于光子晶体的全光逻辑与门和或门。这些新设计的逻辑门在 1550 nm 的电信波长下运行,与现有设计相比,功耗非常低。基本的全光逻辑门级联起来作为通用门 NAND 和 NOR。根据半径和晶格常数等结构参数,对响应时间、对比度和足迹等各种参数进行分析和优化。所提出的结构在 1 $$\upmu$$ μ W 范围内具有非常低的功耗,与门的占位面积为 168 $$\upmu \mathrm{m}^2$$ μ m 2 和 150 $$ \upmu \mathrm{m}^2$$ μ m 2 分别用于或门。所提出的与门的对比度值为 8.45 dB。OR 门的响应时间为 0.4 ps,AND 门的响应时间为 0.16 ps,因此比特率高达 6.25 Tbps。NAND 和 NOR 门的级联操作获得的对比度分别为 5.29 dB 和 5.3 dB。所提出的门的带隙图是使用平面波扩展方法获得的,并且使用有限差分时域技术研究了它们的性能。此外,德摩根定律的实现是通过级联提出的全光逻辑门并因此验证其真值表来实现的。所提出的门的带隙图是使用平面波扩展方法获得的,并且使用有限差分时域技术研究了它们的性能。此外,德摩根定律的实现是通过级联提出的全光逻辑门并因此验证其真值表来实现的。所提出的门的带隙图是使用平面波扩展方法获得的,并且使用有限差分时域技术研究了它们的性能。此外,德摩根定律的实现是通过级联提出的全光逻辑门并因此验证其真值表来实现的。
更新日期:2020-05-27
down
wechat
bug