It has always been difficult to balance the accuracy and performance of ISSs. RTL simulators or systems such as gem5 are used to execute programs in a cycle-accurate manner but are often prohibitively slow. In contrast, functional simulators such as QEMU can run large benchmarks to completion in a reasonable time yet capture few performance metrics and fail to model complex interactions between multiple cores. This paper presents a novel multi-purpose simulator that exploits binary translation to offer fast cycle-level full-system simulations. Its functional simulation mode outperforms QEMU and, if desired, it is possible to switch between functional and timing modes at run-time. Cycle-level simulations of RISC-V multi-core processors are possible at more than 20 MIPS, a useful middle ground in terms of accuracy and performance with simulation speeds nearly 100 times those of more detailed cycle-accurate models.

中文翻译：

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使用二进制转换加速多核 RISC-V 系统的周期级全系统仿真

国际空间站的准确性和性能一直很难平衡。RTL 模拟器或系统（例如 gem5）用于以周期精确的方式执行程序，但通常速度非常慢。相比之下，QEMU 等功能模拟器可以在合理的时间内完成大型基准测试，但捕获的性能指标很少，并且无法对多个内核之间的复杂交互进行建模。本文提出了一种新颖的多用途模拟器，它利用二进制翻译来提供快速的循环级全系统模拟。它的功能模拟模式优于 QEMU，如果需要，可以在运行时在功能模式和计时模式之间切换。RISC-V 多核处理器的周期级模拟可以超过 20 MIPS，