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A 2.4 mW, +11.3 dBm IIP3 and 17 dB conversion gain CMOS mixer with capacitor cross-coupled and modified post distortion techniques
AEU - International Journal of Electronics and Communications ( IF 3.0 ) Pub Date : 2020-05-24 , DOI: 10.1016/j.aeue.2020.153246
Lai Chi Yi , Harikrishnan Ramiah , Nandini Vitee , Jagadheswaran Rajendran

This paper presents a novel design of a double-balanced folded mixer for ISM applications. By utilizing the capacitor cross-coupled (CCC) topology and a modified post distortion (PD) technique in the transconductance stage, a high linearity mixer is realized with lower power dissipation. The mixer is designed and fabricated in a 0.13-µm CMOS process, operating in the frequency band of 900 MHz. Measurement results indicate a conversion gain of 17 dB, a high third-order input intercept point (IIP3) of 11.3 dBm and a noise figure (NF) of 10 dB. Also, the folded structure allows the mixer to operate under 1.0-V supply voltage with a power dissipation of only 2.4 mW.



中文翻译:

具有电容器交叉耦合和修改后失真技术的2.4 mW,+ 11.3 dBm IIP3和17 dB转换增益CMOS混频器

本文介绍了一种适用于ISM应用的双平衡折叠式混频器的新颖设计。通过在跨导级中利用电容器交叉耦合(CCC)拓扑和改进的后失真(PD)技术,可以实现具有较低功耗的高线性度混频器。该混频器采用0.13 µm CMOS工艺进行设计和制造,工作在900 MHz频段。测量结果表明转换增益为17 dB,高三阶输入截取点(IIP3)为11.3 dBm,噪声系数(NF)为10 dB。同样,折叠结构使混频器可以在1.0V电源电压下工作,功耗仅为2.4mW。

更新日期:2020-05-24
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