The experimental data on the plasma etching of Si 3 N 4 for sub-100 nm gate fabrication for high electron mobility transistors (HEMTs) based on InAlN/GaN heterostructures are analyzed. The influence of the plasma etching process parameters on the plasma-induced damage to the InAlN/GaN heterostructure is considered. The possibility of formation of a 70 nm-length gate InAlN/GaN HEMT using low damage reactive ion etching of Si 3 N 4 is demonstrated.

中文翻译：

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InAlN/GaN Hemt 技术中的等离子体蚀刻

分析了用于基于 InAlN/GaN 异质结构的高电子迁移率晶体管 (HEMT) 的亚 100 nm 栅极制造的 Si 3 N 4 等离子体蚀刻实验数据。考虑了等离子体蚀刻工艺参数对等离子体诱导的 InAlN/GaN 异质结构损伤的影响。证明了使用 Si 3 N 4 的低损伤反应离子蚀刻形成 70 nm 长栅极 InAlN/GaN HEMT 的可能性。