A novel PNP-triggered dynamic substrate GGNMOS (gate-grounded NMOS) structure is proposed and verified in 0.18 μm salicided CMOS process. Owing to the dynamic substrate technique and imbedded PNP transistor which injects triggering current to the substrate under ESD (electrostatic discharge) events, the proposed structure features a small trigger voltage, a small snapback region, a high robustness, and a larger margin of ESD design window is achieved. Compared with traditional dynamic substrate GGNMOS, the proposed structure promotes FOM (figure of merit) by 60%. So it is a more feasible solution in ESD protections applications of low-voltage and thin gate oxide process for its overall improved performances.

提出了一种新的PNP触发动态衬底GGNMOS（栅极接地NMOS）结构，并在0.18μm硅化CMOS工艺中进行了验证。由于采用了动态衬底技术和嵌入式PNP晶体管，该衬底在ESD（静电放电）事件下向衬底注入触发电流，因此该结构具有触发电压小，回弹区域小，鲁棒性高以及ESD设计裕度大的特点。窗口已实现。与传统的动态衬底GGNMOS相比，该结构将FOM（品质因数）提高了60％。因此，由于其整体性能的提高，因此在低压和薄栅氧化工艺的ESD保护应用中是一种更可行的解决方案。