In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.

中文翻译：

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堆叠纳米片环栅 MOSFET 中沟道释放过程引起的电特性行为的研究

在本简报中，严格研究了归因于具有各种纳米片 (NS) 宽度的垂直堆叠全环栅 MOSFET (GAAFET) 中的沟道释放过程的几个问题。由于 SiGe（牺牲层）蚀刻剂对 Si（沟道层）的选择性有限，在沟道释放步骤期间，Si 沟道很可能变薄，这是堆叠 GAA FET 制造的关键工艺之一。因此，通道的厚度和通道间空间会根据 NS 宽度而变化，因为蚀刻时间必须由晶片内最宽的通道决定。它导致栅极功函数、栅极-漏极电容、沟道界面特性以及静电栅极可控性的沟道宽度依赖性。通过基于工艺的 3-D 技术计算机辅助设计 (TCAD) 器件模拟以及透射电子显微镜 (TEM) 和能量色散谱 (EDS)，彻底研究了由这些效应引起的堆叠 GAAFET 的电气特性行为分析。结果证实，在制造和紧凑建模具有逻辑和静态随机存取存储器 (SRAM) 应用所需的各种 NS 宽度的堆叠 GAAFET 时，应考虑宽度相关效应。