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Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-level 3D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( IF 2.7 ) Pub Date : 2020-06-01 , DOI: 10.1109/tcad.2019.2952542
Bon Woong Ku , Kyungwook Chang , Sung Kyu Lim

The recent advancement of wafer bonding and monolithic integration technology offers fine-grained 3-D interconnections to face-to-face (F2F) and monolithic 3-D (M3D) ICs. In this article, we propose a full-chip RTL-to-GDSII physical design solution to build commercial-quality two-tier gate-level F2F and M3D ICs. The state-of-the-art flow named shrunk-2D (S2D) requires shrinking of standard cells and interconnects by a factor of 50% to fit into the target 3-D footprint of a two-tier design. This, unfortunately, necessitates commercial place/route engines that handle one node smaller geometries, which can be challenging and costly. Our flow named compact-2D (C2D) does not require any geometry shrinking. Instead, C2D implements a 2-D IC with scaled interconnect $RC$ parasitics and contracts the layout to the 3-D integrated circuit footprint. In addition, C2D offers post-tier-partitioning optimization (post-TP opt) which is completely missing in S2D. This additional optimization step is shown to be effective in fixing timing violations caused by intertier 3-D routing overhead. Lastly, we present a methodology to reuse the routing result of post-TP opt for the final GDSII generation. Our experimental results show that at iso-performance, C2D offers up to 28.0% power reduction and 15.6% silicon area savings over commercial 2-D ICs without any routing resource overhead.

中文翻译:

Compact-2D:一种构建两层门级 3D IC 的物理设计方法

晶圆键合和单片集成技术的最新进展为面对面 (F2F) 和单片 3-D (M3D) IC 提供了细粒度的 3-D 互连。在本文中,我们提出了一种全芯片 RTL-to-GDSII 物理设计解决方案,以构建商业品质的两层门级 F2F 和 M3D IC。名为 shrunk-2D (S2D) 的最先进流程需要将标准单元和互连缩小 50%,以适应两层设计的目标 3D 封装。不幸的是,这需要商业布局/布线引擎来处理一个节点较小的几何图形,这可能具有挑战性且成本高昂。我们名为 compact-2D (C2D) 的流程不需要任何几何收缩。相反,C2D 实现了一个 2-D IC,具有缩放互连 $RC$ 寄生参数,并将布局收缩到 3-D 集成电路封装。此外,C2D 提供了 S2D 中完全没有的后层分区优化(post-TP opt)。这个额外的优化步骤被证明可以有效地修复由层间 3-D 路由开销引起的时序违规。最后,我们提出了一种方法来重用 post-TP opt 的路由结果来生成最终的 GDSII。我们的实验结果表明,在同等性能​​下,C2D 与商用 2-D IC 相比,可降低高达 28.0% 的功耗和 15.6% 的硅面积节省,而无需任何布线资源开销。我们提出了一种方法来重用 post-TP opt 的路由结果来生成最终的 GDSII。我们的实验结果表明,在同等性能​​下,C2D 与商用 2-D IC 相比,可降低高达 28.0% 的功耗和 15.6% 的硅面积节省,而无需任何布线资源开销。我们提出了一种方法来重用 post-TP opt 的路由结果来生成最终的 GDSII。我们的实验结果表明,在同等性能​​下,C2D 与商用 2-D IC 相比,可降低高达 28.0% 的功耗和 15.6% 的硅面积节省,而无需任何布线资源开销。
更新日期:2020-06-01
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