A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS’89 and ITC’99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs.

中文翻译：

---

在一次 ATPG 运行中为多个 CMOS 故障模型生成单模式和双模式测试

提出了一种针对多个直流和交流故障的新型测试模式生成方法。所考虑的故障模型包括线路卡住、桥接、转换和晶体管卡住开路故障。所有故障都被转换为固定故障，并在提出的双时间帧电路模型中具有一些约束，这样所有考虑的故障都可以使用当前大多数商业 ATPG 工具支持的用户定义故障模型来表示。这使得在一次 ATPG 运行中为直流和交流故障生成一组紧凑的模式成为可能，而无需修改 ATPG 工具。支持在捕获时发射和在换档时发射两种测试方法。ISCAS'89 和 ITC'99 基准电路的实验结果表明，与早期 PM 相比，所提出的方法 (PM) 的有效性。