Approximate computing is an emerging circuit design technique which reduce the energy consumption with acceptable degradation in accuracy. Three approximate radix-8 Booth multipliers are proposed in this paper to explore the advantages of approximate computing. These multipliers are designed by using two proposed approximate Booth encoders for the generation of approximate partial products. Approximate partial products are introduced into a few number of least significant columns (AC) of the partial product matrix. The proposed multipliers with 16-bit inputs are simulated using a 45-nm CMOS technology library. For AC = 16, the results indicate that the first proposed multiplier reduces power delay product (PDP) and Area by 33% and 23% respectively as compared to conventional radix-8 Booth multiplier. Moreover, it has a Normalized Mean Error Distance (NMED) of 1.43E-5. The second proposed multiplier shows 43% and 31% reduction in PDP and Area respectively with an NMED of 1.664E-5. Similarly, the third proposed multiplier shows 37% and 25% reduction in PDP and Area respectively with an NMED of 1.512E-5. The accuracy of proposed multipliers are verified with real-time applications in image processing and deep learning.

近似计算是一种新兴的电路设计技术，可降低能耗并降低精度。本文提出了三个近似的radix-8 Booth乘法器，以探索近似计算的优势。通过使用两个建议的近似Booth编码器来设计这些乘法器，以生成近似的部分乘积。将近似的部分产品引入部分产品矩阵的几个最低有效列（AC）中。拟议的具有16位输入的乘法器使用45纳米CMOS技术库进行了仿真。对于AC = 16，结果表明，与传统的radix-8 Booth乘法器相比，第一个建议的乘法器将功率延迟乘积（PDP）和面积分别降低了33％和23％。此外，它的标准化平均误差距离（NMED）为1.43E-5。建议的第二个乘数显示NDP为1.664E-5时，PDP和面积分别减少43％和31％。同样，第三个提议的乘数显示PDP和面积分别减少了37％和25％，NMED为1.512E-5。提出的乘法器的准确性已在图像处理和深度学习中的实时应用中得到验证。