The growth of the blockchain-based cryptocurrencies has attracted a lot of attention from a variety of fields, especially in academic research. One of them is Bitcoin, the most popular and highest valued cryptocurrency on the market. The SHA256 is the main processing part in Bitcoin mining, to date the difficulty of which is extremely high and still increases relentlessly. Hence, it is essential to improve the speed of the SHA256 cores in the Bitcoin mining system. In this paper, we propose a two-level pipeline hardware architecture for the SHA256 processing. The first-level pipeline helps the system reduce the number of operating cycles. Besides, the maximum frequency of the system is boosted by the second-level pipeline. The proposed hardware is implemented on FPGA Xilinx Virtex 7-VC707 (28 nm technology). The mining hash rate using the proposed pipeline SHA256 cores reaches 514.92 MH/s that improves 2.4 times compared to the FPGA based conventional technique. The throughput of SHA core of current study is 296.108 Gbps that is 240 times higher compared to the standard technique. The proposed architecture is also implemented in an ASIC design using ROHM 180 nm CMOS technology, which resulted in a throughput of 69.28 Gbps that is 18 times higher than that of conventional work implemented in Intel 14 nm process.

基于区块链的加密货币的增长吸引了许多领域的关注，尤其是在学术研究中。其中之一就是比特币，它是市场上最受欢迎，价值最高的加密货币。SHA256是比特币挖掘的主要处理部分，迄今为止，其难度非常高，并且仍在不断增加。因此，至关重要的是提高比特币采矿系统中SHA256内核的速度。在本文中，我们提出了用于SHA256处理的两级流水线硬件体系结构。一级管线有助于系统减少操作周期数。此外，系统的最大频率由二级流水线提高。拟议的硬件在FPGA Xilinx Virtex 7-VC707（28 nm技术）上实现。使用建议的管线SHA256内核的挖掘哈希率达到514.92 MH / s，与基于FPGA的常规技术相比提高了2.4倍。当前研究的SHA核心的吞吐量为296.108 Gbps，是标准技术的240倍。所提出的体系结构还使用ROHM 180 nm CMOS技术在ASIC设计中实现，这导致69.28 Gbps的吞吐量是英特尔14 nm工艺中实现的传统工作的18倍。