This paper presents input bias current (I_bias) reduction technique for high impedance CMOS op‐amps with the proposed current compensation circuit to deal with the leakage current caused by Electro‐Static Discharge (ESD) protection circuit of the IC. High input impedance CMOS op‐amps are widely used for the application of high precision sensors with quite small input current. However, the leakage current of ESD protection circuit for op‐amp causes a nonideality error of the I_bias. Especially, the ESD leakage current increases drastically at the high temperature environment, and hence the I_bias of CMOS op‐amp also increased significantly. An ESD leakage current compensation circuit is introduced to reduce the I_bias of CMOS op‐amp. The prototype amplifier with the proposed current compensation circuit is designed and fabricated in standard 0.7 µm CMOS technology. Measurement results show that the I_bias is reduced to a 100 pA or less from a typical 2.3 nA at 150°C.

中文翻译：

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标准CMOS技术中用于运算放大器的输入偏置电流降低技术

本文呈现的输入偏置电流（我_偏压）降低技术用于高阻抗CMOS运算放大器与所提出的电流补偿电路来处理所造成的IC的静电放电（ESD）保护电路的漏电流。高输入阻抗CMOS运算放大器广泛用于输入电流很小的高精度传感器的应用。但是，用于运放的ESD保护电路的泄漏电流会引起I _bias的非理想误差。特别地，ESD漏电流急剧增加，在高温环境中，因此，我_偏压CMOS运算放大器也显著增加。引入了ESD泄漏电流补偿电路以减少我_偏置CMOS运算放大器。带有建议的电流补偿电路的原型放大器采用标准的0.7 µm CMOS技术进行设计和制造。测量结果表明，I_偏置从150°C下的典型2.3 nA降低到100 pA或更小。