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High throughput and low area architectures of secure IoT algorithm for medical image encryption
Journal of Information Security and Applications ( IF 3.8 ) Pub Date : 2020-05-16 , DOI: 10.1016/j.jisa.2020.102533
Zeesha Mishra , Bibhudendra Acharya

The favor that lightweight encryption algorithms have gained over the recent years regarding data and image security in a resource constrained environment of the smart device sort in Internet of Things (IoT) is undeniable. Secure IoT (SIT) is a popular encryption algorithm that tends to consume less hardware resources due to simple operation, which serves a welcome advantage, since it is precisely the reduction of area and power consumption. In this paper, high-speed and low-area architectures are proposed for SIT algorithm under resource constrained applications. The proposed pipelined architecture is useful in high frequency applications, and proposed serial architecture is useful for low area requirement, leads to reduce the cost incurred on hardware. The proposed design can support four different block sizes of an input medical ultrasonic image, namely 32 × 32, 64 × 64, 128 × 128 and 256 × 256 along with Finite State Machine (FSM) controller. The dynamic size of block selection technique saves significant amount of clock cycles during image encryption. The proposed designs have implemented in FPGA XC5VLX50T-3ff1136 device and achieved maximum operating frequency of 287.51 MHz in pipelined architecture and number of slices 46 in serial architecture. PRESENT is an efficient lightweight block cipher having 73 slices in serial architecture whereas proposed serial architecture provides 58.69% improvement in area. LEA is a popular Feistel block cipher generates maximum frequency of 217 MHz in pipelined architecture, but at the same time proposed pipelined architecture provides 32.25% enhancement in speed.



中文翻译:

用于医学图像加密的安全IoT算法的高吞吐量和低面积架构

近年来,轻量级加密算法在物联网(IoT)中智能设备类型的资源受限环境中的数据和图像安全性方面获得了青睐。安全物联网(SIT)是一种流行的加密算法,由于操作简单,往往会消耗较少的硬件资源,这是一个受欢迎的优势,因为它恰恰是减小了面积并降低了功耗。本文针对资源受限的应用,提出了SIT算法的高速低区域架构。所提出的流水线架构可用于高频应用,而所提出的串行架构可用于低面积需求,从而降低了硬件成本。所提出的设计可以支持输入医学超声图像的四个不同块大小,即32×32、64×64、128×128和256×256以及有限状态机(FSM)控制器。块选择技术的动态大小可在图像加密期间节省大量时钟周期。拟议的设计已在FPGA XC5VLX50T-3ff1136器件中实现,并在流水线架构中实现了287.51 MHz的最大工作频率,在串行架构中实现了片46的最大工作频率。PRESENT是一种高效的轻量级分组密码,在串行体系结构中具有73个切片,而所提出的串行体系结构可将面积提高58.69%。LEA是流行的Feistel块密码,在流水线架构中可生成217 MHz的最大频率,但与此同时,建议的流水线架构提供了32个频率。

更新日期:2020-05-16
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