This paper presents a high-sensitivity high-speed dynamic voltage comparator, which is a key component for low power CMOS mixed signal applications. The proposed dynamic comparator employs ten transistors with only one cross-coupled latch to reduce the circuit complexity. The parallel clocked input switches reduce parasitic resistance in the latch ground path that results in a significant decrease in latch delay time. In addition, a symmetric, three stacked transistor, single stage architecture reduces the process variation effects, increases input sensitivity and provides more head room for low power-supply applications. The proposed design is implemented in 90 nm CMOS with 1.2 V power supply and 0.6 V reference voltage, and it provides 30 μV resolution, 105.6 μW power consumption at 2 GHz clock frequency.

本文介绍了一种高灵敏度高速动态电压比较器，它是低功耗CMOS混合信号应用的关键组件。拟议的动态比较器采用十个晶体管，只有一个交叉耦合的锁存器，以降低电路复杂度。并行时钟输入开关降低了锁存器接地路径中的寄生电阻，从而大大降低了锁存器延迟时间。此外，对称的三层堆叠晶体管单级架构减少了工艺变化的影响，提高了输入灵敏度，并为低功耗应用提供了更多的净空。拟议的设计在具有1.2 V电源和0.6 V参考电压的90 nm CMOS中实现，并且在2 GHz时钟频率下提供30μV的分辨率和105.6μW的功耗。